Information processing apparatus such as server, which is expected to be highly reliable, may use an ECC (Error-Correcting Code) in data transmission over a connection bus with another information processing apparatus or between internal devices of the own apparatus. A bus used for data transmission using an ECC is called “ECC bus”, which enables a receiving side of data to perform single-bit error detection and correction, and double-bit error detection.
To check an ECC bus for an error, one example technique is to expressly change transmit data with a dedicated program or hardware device, and confirm whether the data is received without fail at a receiving side. For example, there are two methods for this technique. One method is to send a pattern having changed bits and compare this pattern with an expected pattern at a receiving side during error checking time. However, the error check according this method may not be performed simultaneously with error detection using ECC. The other method is to send transmit data while changing the values of its bits a little at a time (for example, one bit by one bit) and confirm whether the data is received without fail at a receiving side. However, this method needs to prepare patterns of such transmit data as to obtain different ECC patterns.
Another technique to check an ECC bus for an error is to invert only one bit of a signal on a data part or ECC part of a bus, send the signal to the bus, and confirm that an error is detected at a receiving side. FIG. 21 illustrates an example configuration of a system to which this technique is implemented.
FIG. 21 is an example configuration of information processing apparatuses provided with a bus error checking function. In the illustrated configuration, information processing apparatuses are connected to each other with an ECC bus. A transmitting apparatus 910 that is an information processing apparatus of signal transmitting side includes a bus arbitration circuit 911, an inversion control circuit 912, a bus inversion circuit 913, an output circuit 914, and an error detection circuit 915.
The bus arbitration circuit 911 is connected to internal circuits with a plurality of buses. The bus arbitration circuit 911 selects one of transmit signals received from these buses, and outputs the selected transmit signal to the bus inversion circuit 913. The inversion control circuit 912 instructs the bus inversion circuit 913 which bit of a signal is to be inverted. The bus inversion circuit 913 inverts the specified bit of the transmit signal received from the bus arbitration circuit 911, as instructed by the inversion control circuit 912. The output circuit 914 sends the signal received from the bus inversion circuit 913 to a receiving apparatus 920 over the ECC bus. The error detection circuit 915 detects an error in the signal input to the output circuit 914.
On the other hand, the receiving apparatus 920 that is an information processing apparatus of signal receiving side includes an inversion control circuit 921, a bus inversion circuit 922, a receiving circuit 923, and an error detection circuit 924.
The inversion control circuit 921 instructs the bus inversion circuit 922 which bit of a signal is to be inverted. The bus inversion circuit 922 inverts the specified bit of a signal received from the transmitting apparatus 910, as instructed by the inversion control circuit 921. The receiving circuit 923 outputs the signal received from the bus inversion circuit 922 to internal circuits of the receiving apparatus 920. The error detection circuit 924 performs error detection and correction on the signal input to the receiving circuit 923.
To check the ECC bus connecting the transmitting apparatus 910 and the receiving apparatus 920 for an error, either one of the bus inversion circuit 913 of the transmitting apparatus 910 and the bus inversion circuit 922 of the receiving apparatus 920 inverts one bit of a signal. If the ECC bus has not failed, the error detection circuit 924 of the receiving apparatus 920 detects a single-bit error. If the ECC bus has failed, however, the error detection circuit 924 does not detect any errors or detects a double-bit error.
A double-bit error, which is detected by the error detection circuit 924, indicates that an error has occurred in a bus line different from the one which carried an inverted bit of a signal. If a double-bit error is detected, the error detection circuit 924 is not capable of correcting the received signal. This error checking technique may cause a correction failure error accordingly. Therefore, this error check may not be performed during the normal system operation.
By the way, there is a technique for error correction using bit inversion, in which a plurality of syndrome data corresponding to respective single-bit errors of received data are stored, data obtained by inverting one bit of actually received data is compared with the data based on the stored syndrome, and positions for three-bit error correction are located.
Further, there is a technique for data transmission test using bit inversion, in which a BIST (Built In Self Test) circuit is used to selectively invert a plurality of test data, a test data value sequence obtained by logically combining the resulting data is output, and then it is confirmed whether the sequence agrees with an expected value.
Still further, there is a system for transmitting data with a dual encoding technique, in which ground bounce is suppressed by inverting and transmitting data if the number of bits changed from previous data is greater than a prescribed value.
For example, please refer to Japanese Laid-open Patent Publication No. 2002-26741, and Japanese National Publications of International Patent Applications Nos. 2008-541059 and 2007-526574.
The above-described ECC bus error checking techniques have a common problem that the error check may not be performed during the normal system operation because special data for error check need to be prepared and sent in advance or because there is a possibility of detection of uncorrectable double-bit errors.